Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be improved as the transistor size decreases.
A fin field-effect transistor (FinFET) is a type of transistor that lends itself to the dual goals of reducing transistor size while increasing transistor performance. The FinFET is a three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET the transistor channel is formed along the vertical sidewalls of the fin or on both vertical sidewalls and the top horizontal plane of the fin, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
Formation of FinFETs generally first involves fin formation on or in a semiconductor substrate. The fins are uniformly formed across a surface of the semiconductor substrate, but it is often desirable to selectively remove portions of the fins for various chip layout/architecture considerations, thereby producing a tapered configuration whereby a region of longer fins are disposed adjacent to a region of shorter fins. In particular, selective removal of portions of the fins is generally conducted by patterning a mask over the fins to expose portions of the fins to be removed, followed by isotropic etching with an etchant that is selective to the semiconductor material of the fins. Gate electrode structures are uniformly formed over the fins in an array. Thus, some gate electrode structures are disposed over both the longer fins and the shorter fins and some gate electrode structures are disposed only over the longer fins. Additionally, one of the gate electrode structures is disposed over the longer fins and over ends of the shorter fins to effectively “tuck” or bury the ends of the shorter fins beneath the gate electrode structures, thereby masking the ends of the shorter fins to avoid epitaxial growth of semiconductor material at the ends of the shorter fins during further front-end-of-line (FEOL) fabrication techniques.
While it is desirable to completely cover or mask the ends of the shorter fins beneath the gate electrode structures, sharp definition of fin ends for the shorter fins is difficult to achieve, primarily due to etch selectivities during selective removal of portions of the fins. As a result and as illustrated schematically in FIG. 1, the shorter fins 112 may have unpredictable and non-uniform lengths. With the unpredictable and non-uniform lengths of the shorter fins 112, masking the ends 114 of the shorter fins 112 may be difficult or impossible, thereby leaving ends 114 of the shorter fins 112 exposed after formation of the gate electrode structure 116. As schematically illustrated in FIG. 2, unwanted epitaxial growth of semiconductor material 118 may occur at the unmasked ends 114 of the shorter fins 112 during subsequent FEOL fabrication techniques.
Accordingly, it is desirable to fabricate FinFETs having fins with a tapered configuration where a predictable and substantially uniform fin length of the shortened fins is obtained to enable the ends of the shorter fins to be buried beneath the gate electrode structure. In addition, it is desirable to provide FinFET devices having fins with a tapered configuration and with ends of the shorter fins tucked beneath the gate electrode structure. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.